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SN74AUP1G08DCKRG4 数据表(PDF) 2 Page - Texas Instruments

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部件名 SN74AUP1G08DCKRG4
功能描述  LOW-POWER SINGLE 2-INPUT POSITIVE-AND GATE
Download  17 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN74AUP1G08DCKRG4 数据表(HTML) 2 Page - Texas Instruments

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
µA)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time − ns
AUP1G08 data at CL = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
1
2
4
A
B
Y
SN74AUP1G08
LOW-POWER SINGLE 2-INPUT POSITIVE-AND GATE
SCES502G – NOVEMBER 2003 – REVISED OCTOBER 2007
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoFree™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G08YFPR
PREVIEW
0.23-mm Large Bump – YFP (Pb-free)
NanoFree™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G08YZPR
_ _ _HE_
0.23-mm Large Bump – YZP (Pb-free)
–40
°C to 85°C
SON – DRY
Reel of 5000
SN74AUP1G08DRYR
PREVIEW
SOT (SOT-23) – DBV
Reel of 3000
SN74AUP1G08DBVR
H08_
SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G08DCKR
HE_
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G08DRLR
(1)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3)
DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
⋅ = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
L
L
L
L
H
L
H
L
L
H
H
H
LOGIC DIAGRAM (POSITIVE LOGIC)
2
Submit Documentation Feedback
Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G08


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