© 2007 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN2103 Rev. 1.0.3

3

Pin Configuration

Figure 3. MLP 5x6mm Pin Configuration (Bottom View)

Pin Definitions

Pin

Name

Description

P1, 6-12

SW

Switching Node

.

P2, 2-5

VIN

Power Input Voltage

. Connect to the main input power source.

P3, 21-23

PGND

Power Ground

. Power return and Q2 source.

1

BOOT

High-side Drive BOOT Voltage

SW is LOW.

13

PGOOD

Power-Good Flag

. An open-drain output that pulls LOW when FB is outside a ±10% range

of the reference when EN is HIGH. PGOOD does not assert HIGH until the fault latch is

enabled.

14

EN

ENABLE

. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the

regulator after a latched fault condition. This input has an internal pull-up when the IC is

functioning normally. When a latched fault occurs, EN is discharged by a current sink.

15

VCC

Input Bias Supply for IC

. The IC’s logic and analog circuitry are powered from this pin.

16

AGND

Analog Ground

. The signal ground for the IC. All internal control voltages are referred to

this pin. Tie this pin to the ground island/plane through the lowest impedance connection.

17

ILIM

Current Limit

limit trip threshold lower than the default setting.

18

R(T)

Oscillator Frequency

frequency.

19

FB

Output Voltage Feedback

. Connect through a resistor divider to the output voltage.

20

COMP

Compensation

. Error amplifier output. Connect the external compensation network

between this pin and FB.

24

PWM#

Power Save Mode / Forced PWM

of operation. Connect to GND or leave open for fixed-frequency PWM mode.

25

RAMP

Ramp Amplitude

amplitude and provides voltage feedforward functionality.