AD7984

Rev. 0 | Page 5 of 24

TIMING SPECIFICATIONS

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

300

500

ns

Acquisition Time

250

ns

Time Between Conversions

750

ns

CNV Pulse Width (CS Mode)

10

ns

SCK Period (CS Mode)

VIO Above 4.5 V

10.5

ns

VIO Above 3 V

12

ns

VIO Above 2.7 V

13

ns

VIO Above 2.3 V

15

ns

SCK Period (Chain Mode)

VIO Above 4.5 V

11.5

ns

VIO Above 3 V

13

ns

VIO Above 2.7 V

14

ns

VIO Above 2.3 V

16

ns

SCK Low Time

4.5

ns

SCK High Time

4.5

ns

SCK Falling Edge to Data Remains Valid

3

ns

SCK Falling Edge to Data Valid Delay

VIO Above 4.5 V

9.5

ns

VIO Above 3 V

11

ns

VIO Above 2.7 V

12

ns

VIO Above 2.3 V

14

ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 3 V

10

ns

VIO Above 2.3 V

15

ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

20

ns

SDI Valid Setup Time from CNV Rising Edge

5

ns

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

2

ns

SDI Valid Hold Time from CNV Rising Edge (Chain Mode)

0

ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

5

ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

5

ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

2

ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

3

ns

SDI High to SDO High (Chain Mode with Busy Indicator)

15

ns

500µA

500µA

1.4V

TO SDO

20pF

Figure 2. Load Circuit for Digital Interface Timing

SPECIFICATIONS IN TABLE 3.

Figure 3. Voltage Levels for Timing