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74VHCT16373ATTR 数据表(PDF) 1 Page - STMicroelectronics |
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74VHCT16373ATTR 数据表(HTML) 1 Page - STMicroelectronics |
1 / 10 page 1/10 February 2003 s HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN.) VIL = 0.8 (MAX.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.9V (MAX.) DESCRIPTION The 74VHCT16373A is an advanced high-speed CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(nOE). While the nLE input is held at a high level, the nQ outputs will follow the data (D) inputs. When the nLE is taken LOW, the nQ outputs will be latched at the logic level of D data inputs. When the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level); when nOE is at high level ,the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74VHCT16373A 16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING ORDER CODES PACKAGE TUBE T & R TSSOP 74VHCT16373ATTR TSSOP PIN CONNECTION |
类似零件编号 - 74VHCT16373ATTR |
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类似说明 - 74VHCT16373ATTR |
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