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TC74VHC138FT 数据表(PDF) 1 Page - Toshiba Semiconductor |
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TC74VHC138FT 数据表(HTML) 1 Page - Toshiba Semiconductor |
1 / 10 page TC74VHC138F/FN/FT/FK 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC138F,TC74VHC138FN,TC74VHC138FT,TC74VHC138FK 3-to-8 Line Decoder The TC74VHC138 is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( 0 Y- 7 Y ) will go low. When enable input G1 is held low or either 2A G or 2B G is held high, decoding function is inhibited and all outputs go high. G1, 2A G , and 2B G inputs are provided to ease cascade connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features • High speed: tpd = 5.7 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Power down protection is provided on all inputs. • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 V to 5.5 V • Pin and function compatible with 74ALS138 Weight SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) VSSOP16-P-0030-0.50 : 0.02 g (typ.) Note: xxxFN (JEDEC SOP) is not available in Japan. TC74VHC138F TC74VHC138FN TC74VHC138FT TC74VHC138FK |
类似零件编号 - TC74VHC138FT |
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类似说明 - TC74VHC138FT |
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