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CDCUA877ZQL 数据表(PDF) 7 Page - Texas Instruments |
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CDCUA877ZQL 数据表(HTML) 7 Page - Texas Instruments |
7 / 16 page www.ti.com SWITCHING CHARACTERISTICS CDCUA877 SCAS769A – AUGUST 2006 – REVISED JUNE 2007 over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ten Enable time, OE to any Y/Y See Figure 12 8 ns tdis Disable time, OE to any Y/Y See Figure 12 8 ns tjit(cc+) 0 40 Cycle-to-cycle period jitter(2) 160 MHz to 410 MHz, See Figure 5 ps tjit(cc-) 0 –40 t(φ) Static phase offset time(3) See Figure 6 –50 50 ps t(φ)dyn Dynamic phase offset time,(4) See Figure 11 –20 20 ps tsk(o) Output clock skew(4) See Figure 7 35 ps 160 MHz to 270 MHz, see Figure 8 –30 30 tjit(per) Period jitter (2)(5) ps 271 MHz to 410 MHz, see Figure 8 –20 20 160 MHz to 270 MHz, see Figure 9 –75 75 tjit(hper) Half-period jitter (2) (5) ps 271 MHz to 410 MHz, see Figure 9 –50 50 Σt(su) |tjit(per)| + |t(φ)dyn| + tsk(o) (6) 271 MHz to 410 MHz 80 ps Σt(h) |t(φ)dyn| + + tsk(o) (6) 271 MHz to 410 MHz 60 ps Slew rate, OE See Figure 3 and Figure 8 0.5 SR Input clock skew rate See Figure 3 and Figure 8 1 2.5 4 V/ns Output clock slew rate(7)(8) See Figure 3 and Figure 8 1.5 2.5 3 Output differential-pair cross VOX See Figure 2 (VDDQ/2) – 0.1 (VDDQ/2) + 0.1 V voltage(9) SSC modulation frequency 30 33 kHz SSC clock input frequency 0% –0.5% deviation PLL loop bandwidth 2 MHz (1) There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. (2) This parameter is assured by design and characterization. (3) Phase static offset time does not include jitter. (4) For full frequency range of 160MHz to 410MHz. (5) Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. (6) In the frequency range of 271 MHz to 410 MHz, the minimum and maximum values of tjit(per) and t(φ)dyn and the maximum value for tsk(o) must not exceed the corresponding minimum and maximum values of the 160 MHz to 270 MHz range. In addition, the sum of the specified values for |tjit(per)|, |t(φ)dyn|, and tsk(o) must meet the requirements for the Σt(su) and the sum of the specified values for |t(φ)dyn| and tsk(o) must meet the requirements for the Σt(h). (7) The output slew rate is determined from the IBIS model into the load shown in Figure 4. (8) To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. (9) Output differential-pair cross voltage specified at the DRAM clock input or the test load. 7 Submit Documentation Feedback |
类似零件编号 - CDCUA877ZQL |
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类似说明 - CDCUA877ZQL |
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