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SN74V3680-15PEU 数据表(PDF) 11 Page - Texas Instruments |
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SN74V3680-15PEU 数据表(HTML) 11 Page - Texas Instruments |
11 / 50 page SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 programmable-flag mode (PFM) During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM selects synchronous programmable-flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM low during MRS), PAE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, PAF is asserted low on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. If synchronous PAE/PAF configuration is selected (PFM high during MRS), PAE is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the PFM. interspersed parity (IP) During master reset, a low on IP selects noninterspersed-parity mode. A high selects interspersed-parity mode. The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bits are located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D28 are assumed to be valid bits and D32, D33, D34, and D35 are ignored. IP mode is selected during master reset by the state of the IP input pin. Interspersed-parity control has an effect only during parallel programming of the offset registers. It does not affect the data written to, and read from, the FIFO. outputs full flag/input ready (FF/IR) FF/IR is a dual-purpose pin. In standard mode, the FF function is selected. When the FIFO is full, FF goes low, inhibiting further write operations. When FF is high, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS), FF goes low after D writes to the FIFO (D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for the SN74V3690). See Figure 7 for timing information. In FWFT mode, the IR function is selected. IR goes low when memory space is available for writing in data. When there is no longer any free space left, IR goes high, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR goes high after D writes to the FIFO (D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690). See Figure 9 for timing information. The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in standard mode. FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs. |
类似零件编号 - SN74V3680-15PEU |
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类似说明 - SN74V3680-15PEU |
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