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SM5819AF 数据表(PDF) 11 Page - Nippon Precision Circuits Inc

部件名 SM5819AF
功能描述  6-channel DSD-PCM Converter
Download  18 Pages
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制造商  NPC [Nippon Precision Circuits Inc]
网页  http://www.npc.co.jp/en
标志 NPC - Nippon Precision Circuits Inc

SM5819AF 数据表(HTML) 11 Page - Nippon Precision Circuits Inc

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SM5819AF
SEIKO NPC CORPORATION —11
FUNCTIONAL DESCRIPTION
Data Input/Output Formats
DSD input format
DSD input data is read in on the rising edge of the DSBCK bit clock.
PCM output format
The PCM output format can be assigned to either of two types below using FMTPCM. The output data is in 32-
bit 2s complement form. The PLRCK and PBCK frequencies are set in response to the fs/2fs/4fs switch mode.
However, when external inputs are selected, the inputs are passed to the output in through mode, regardless of
the assigned format.
(1) MSB-first left-justified 32-bit (FMTPCM = “L”)
I
If more than 32 bit clock cycles are input during a word clock cycle HIGH-level or LOW-level pulse, all bits
after the 32nd bit are output as “0”.
I
When PLRCK and PBCK are set to output mode, the number of bit clock cycles during a word clock HIGH-
level or LOW-level pulse is fixed at 32.
(2) IIS 32-bit (FMTPCM = “H”)
I
In this format, there are 32 bit clock cycles per word clock cycle regardless of the input/output settings.
DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins
PO**: POFLR, POSLR, POCSW pins
PO**: POFLR, POSLR, POCSW pins
DSBCK
DSI**
(1/64fs)
PLRCK
(1/fs, 1/2fs, or 1/4fs)
31 30 29 28
MSB
PBCK
PO**
2
1
0
31 30
LSB
29 28
2
1
0
31 30
Lch (POSLR, POFLR)
Center (POCSW)
Rch (POSLR, POFLR)
SubWoofer (POCSW)
PLRCK
(1/fs, 1/2fs, or 1/4fs)
0
31 30 29
4
3
2
0
31 30
MSB
0
31
LSB
PBCK
PO**
29
4
3
2
Rch (POSLR, POFLR)
SubWoofer (POCSW)
Lch (POSLR, POFLR)
Center (POCSW)
1
1
1


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