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74LVC1G80GF 数据表(PDF) 4 Page - NXP Semiconductors |
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74LVC1G80GF 数据表(HTML) 4 Page - NXP Semiconductors |
4 / 16 page 74LVC1G80_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 29 August 2007 4 of 16 NXP Semiconductors 74LVC1G80 Single D-type flip-flop; positive-edge trigger 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level. ↑ = LOW-to-HIGH CP transition; X = don’t care; q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. 8. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of P tot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of P tot derates linearly with 2.4 mW/K. Table 4. Function table[1] Input Output CP D Q ↑ LH ↑ HL LX q Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +6.5 V IIK input clamping current VI < 0 V −50 - mA VI input voltage [1] −0.5 +6.5 V IOK output clamping current VO > VCC or VO < 0 V - ±50 mA VO output voltage Active mode [1][2] −0.5 VCC + 0.5 V Power-down mode [1][2] −0.5 +6.5 V IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current −100 - mA Ptot total power dissipation Tamb = −40 °C to +125 °C [3] - 250 mW Tstg storage temperature −65 +150 °C |
类似零件编号 - 74LVC1G80GF |
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类似说明 - 74LVC1G80GF |
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