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74LV132N 数据表(PDF) 4 Page - NXP Semiconductors |
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74LV132N 数据表(HTML) 4 Page - NXP Semiconductors |
4 / 17 page 74LV132_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 12 November 2007 4 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger 7. Functional description 8. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. [5] Ptot derates linearly with 4.5 mW/K above 60 °C. Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input Output nA nB nY LLH LH H HL H HHL Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7.0 V IIK input clamping current VI < −0.5 V or VI >VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < −0.5 V or VO >VCC + 0.5 V [1] - ±50 mA IO output current VO = −0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C DIP14 package [2] - 750 mW SO14 package [3] - 500 mW (T)SSOP14 package [4] - 500 mW DHVQFN14 package [5] - 500 mW |
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类似说明 - 74LV132N |
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