74AUP2G80GM datasheet(11/18 Pages) NXP

部件名	74AUP2G80GM

功能描述	Low-power dual D-type flip-flop; positive-edge trigger

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制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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11 / 18 page

74AUP2G80_2

Product data sheet

Rev. 02 — 1 August 2007

11 of 18

NXP Semiconductors

74AUP2G80

Low-power dual D-type ﬂip-ﬂop; positive-edge trigger

12. Waveforms

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.

Fig 7.

The clock input (nCP) to output (nQ) propagation delays

001aaf311

nCP input

nQ output

tPLH

tPHL

VM

VOH

VI

GND

nD input

VI

GND

VOL

VM

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.

Fig 8.

The clock input (nCP) to output (nQ) propagation delays, clock pulse width, nD to nCP setup and hold

times and the nCP maximum frequency

001aaf312

th

tsu(L)

th

tPLH

tW

tPHL

tsu(H)

1/fmax

VM

VI

GND

VI

GND

nCP input

nD input

VOH

VOL

nQ output

Table 9.

Measurement points

Supply voltage

Output

Input

VCC

VM

VI

tr = tf

0.8 V to 3.6 V

0.5

× V

CC

0.5

× V

CC

VCC

≤ 3.0 ns

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