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SM5964AIHHKL 数据表(PDF) 5 Page - SyncMOS Technologies,Inc |
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SM5964AIHHKL 数据表(HTML) 5 Page - SyncMOS Technologies,Inc |
5 / 30 page SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. Ver 2.3 SM5964A 10/2006 5 MNEMONIC PDIP 40 pin PQFP 44 Pin PLCC 44 pin Names and Functions ALE 30 27 33 Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted twice every machine cycle, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Setting SFR SCONF.0 can disable ALE. With this bit set, ALE will be active only during a MOVX instruction. #PSEN 29 26 32 Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, #PSEN is activated twice each machine cycle, except that two #PSEN activations are skipped during each access to external data memory. #PSEN is not activated during fetches from internal program memory. #EA 31 29 35 External Access Enable: #EA must be externally held low to enable the device to fetch code from external program memory locations. If #EA is held high, the device executes from internal program memory. X1 19 15 21 Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X2 18 14 20 Crystal 2: Output from the inverting oscillator amplifier. |
类似零件编号 - SM5964AIHHKL |
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类似说明 - SM5964AIHHKL |
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