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SN74AUCH16244DGVR 数据表(PDF) 1 Page - Texas Instruments

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部件名 SN74AUCH16244DGVR
功能描述  16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
Download  15 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN74AUCH16244DGVR 数据表(HTML) 1 Page - Texas Instruments

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SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
 Family
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max tpd of 1.8 ns at 1.8 V
D Low Power Consumption, 20-µA Max ICC
D ±8-mA Output Drive at 1.8 V
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit buffer/driver is operational at 0.8-V to
2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUCH16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AUCH16244DGGR
AUCH16244
–40
°C to 85°C
TVSOP – DGV
Tape and reel
SN74AUCH16244DGVR
MJ244
VFBGA – GQL
Tape and reel
SN74AUCH16244GQLR
MJ244
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments.
DGG OR DGV PACKAGE
(TOP VIEW)
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1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE


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