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ML145428-6P 数据表(PDF) 1 Page - LANSDALE Semiconductor Inc.

部件名 ML145428-6P
功能描述  Asynchronous-to-Synchronous and Synchronous-to-Asynchronous Converter
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制造商  LANSDALE [LANSDALE Semiconductor Inc.]
网页  http://www.lansdale.com
标志 LANSDALE - LANSDALE Semiconductor Inc.

ML145428-6P 数据表(HTML) 1 Page - LANSDALE Semiconductor Inc.

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Issue 0
ML145428
Asynchronous–to–Synchronous
and Synchronous–to–
Asynchronous Converter
Legacy Device: Motorola MC145428
The ML145428 Data Set Interface provides asynchronous-to-synchronous
and synchronous-to-asynchronous data conversion. It is ideally suited for
voice/data digital telesets supplying an EIA-232 compatible data port into a
synchronous transmission link. Other applications include: data multiplexers,
concentrators, data-only switching, and PBX-based local area networks. This
low-power CMOS device directly interfaces with either the 64 kbps or 8kbps
channel of Motorola’s MC145422 and MC145426 Universal Digital Loop
Transceivers (UDLTs), as well as the MC145421 and MC145425 Second
Generation Universal Digital Loop Transceivers (UDLT II).
• Provides the Interface Between Asynchronous Data Ports and
Synchronous Transmission Lines
• Up to 128 kbps Asynchronous Data Rate Operation
• Up to 2.1 Mbps Synchronous Data Rate Operation
• On-Board Bit Rate Clock Generator with Pin Selectable Bit Rates of
300, 1200, 1400, 4800, 9600, 19200 and 38400 bps or an Externally
Supplied 16 Times Bit Rate Clock
• Accepts Asynchronous Data Words of 8 or 9 Bits in Length
• False Start Detection Provided
• Automatic Sync Insertion and Checking
• Single 5 V Power Supply
• Low Power Consumption of 5 mW Typical
• Application Notes AN943 and AN946
• Operating Temperature Range TA = –40º to +85ºC.
P DIP 20 = RP
PLASTIC
CASE 732
SOG 20 = -6P
PLASTIC
CASE 751D
20
1
20
1
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 20
MC145428P
ML145428RP
SOG 20
MC145428DW
ML145428-6P
LANSDALE
PACKAGE
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
BR1
BRCLK
DL
TxD
TxS
VSS
SB
BR3
BR2
BCLK 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
CM
DOE
DCO
RESET
VDD
RxD
RxS
DCI
DIE
DCLK
BLOCK DIAGRAM
DOE
DIE
DCLK
CM
RESET
DCI
TxS
TxD
DL
BR1-BR3
BCLK
BRCLK
RxD
SB
RxS
DATA
STRIPPER
Tx
FIFO
SYNCHRONOUS
CHANNEL
TRANSMITTER
BAUD
RATE
GEN
CONTROL
DATA
FORMATTER
Rx
FIFO
SYNCHRONOUS
CHANNEL
RECEIVER
DCO


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