ML145170EP datasheet(4/26 Pages) LANSDALE

部件名	ML145170EP

功能描述	Phase-Frequency Detector PLL Frequency Synthesizer with Serial Interface

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制造商	LANSDALE [LANSDALE Semiconductor Inc.]

网页	http://www.lansdale.com

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LANSDALE Semiconductor, Inc.

ML145170

www.lansdale.com

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AC INTERFACE CHARACTERISTICS ( TA = –40° to 85°C, CL= 50 pF, Input tr = tr = 10 ns, unless otherwise noted.)

Parameter

Symbol

Figure

No.

VDD

V

Guaranteed

Limit

Unit

Serial Data Clock Frequency (Note: Refer to Clock tw Below)

fclk

1

2.7

4.5

5.5

dc to 3.0

dc to 4.0

MHz

Maximum Propagation Delay, CLK to Dout

tPLH, t

1, 5

2.7

4.5

5.5

150

85

ns

Maximum Disable Time, Dout Active to High Impedance

tPLZ, t

2, 6

2.7

4.5

5.5

300

200

ns

Access Time, Dout High Impedance to Active

t

PZH

2, 6

2.7

4.5

5.5

0 to 200

0 to 100

ns

out

CL = 50 pF

tTLH, t

1, 5

2.7

4.5

5.5

150

50

ns

CL = 200 pF

1, 5

2.7

4.5

5.5

900

150

ns

Maximum Input Capacitance – Din, ENB, CLK

Cin

–

10

pF

Maximum Output Capacitance – Dout

Cout

–

10

pF

TIMING REQUIREMENTS ( TA = –40° to 85°C, Input tr = t = 10 ns, unless otherwise noted.)

Parameter

Symbol

Figure

No.

VDD

V

Guaranteed

Limit

Unit

in

tsu

3

2.7

4.5

5.5

55

40

Minimum Setup, Hold, and Recovery Times, ENB vs CLK

tsu, th, trec

4

2.7

4.5

5.5

135

100

ns

Minimum Inactive–High Pulse Width, ENB

tw(H)

4

2.7

4.5

5.5

400

300

ns

Minimum Pulse Width, CLK

tw

1

2.7

4.5

5.5

166

125

ns

tr, tf

1

2.7

4.5

5.5

100

µs

dc to 4.0

PHL

PHZ

t

Maximum Output Transition Time, D

Minimum Setup and Hold Times, D

vs CLK

Maximum Input Rise and Fall Times, CLK

f

ns

h

PZL

THL

, t

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