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MC145050P 数据表(PDF) 3 Page - LANSDALE Semiconductor Inc. |
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MC145050P 数据表(HTML) 3 Page - LANSDALE Semiconductor Inc. |
3 / 15 page www.lansdale.com Page 3 of 15 LANSDALE Semiconductor, Inc. ML145050, ML145051 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated) Symbol Parameter Test Condition Guaranteed Limit Unit VIH Minimum High-Level Input Voltage (Din, SCLK, CS, ADCLK) 2.0 V VIL Maximum Low-Level Input Voltage (Din, SCLK, CS, ADCLK) 0.8 V VOH Minimum High-Level Output Voltage (Dout, EOC) Iout = – 1.6 mA Iout = – 20 µA 2.4 VDD – 0.1 V VOL Minimum Low-Level Output Voltage (Dout, EOC) Iout = + 1.6 mA Iout = 20 µA 0.4 0.1 V Iin Maximum Input Leakage Current (Din, SCLK, CS, ADCLK) Vin = VSS or VDD + 2.5 µA IOZ Maximum Three-State Leakage Current (Dout) Vout = VSS or VDD + 10 µA IDD Maximum Power Supply Current Vin = VSS or VDD, All Outputs Open 2.5 mA Iref Maximum Static Analog Reference Current (Vref) Vref = VDD, VAG = VSS 100 µA IAl Maximum Analog Mux Input Leakage Current between all deselected inputs and any selected input (AN0 ± AN10) VAl = VSS to VDD + 1 µA A/D CONVERTER ELECTRICAL CHARACTERISTICS (Full Temperature and Voltage Ranges per Operation Ranges Table; ML145050: 500 kHz ≤ ADCLK ≤ 2.1 MHz, unless otherwise noted) Characteristic Definition and Test Conditions Guaranteed Limit Unit Resolution Number of bits resolved by the A/D converter 10 Bits Maximum Nonlinearity Maximum difference between an ideal and an actual ADC transfer function ± 1 LSB Maximum Zero Error Difference between the maximum input voltage of an ideal and an actual ADC for zero output code ± 1 LSB Maximum Full-Scale Error Difference between the minimum input voltage of an ideal and an actual ADC for full-scale output code ± 1 LSB Maximum Total Unadjusted Error Maximum sum of nonlinearity, zero error, and full-scale error ± 1 LSB Maximum Quantization Error Uncertainty due to converter resolution ± 1/2 LSB Absolute Accuracy Difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all error sources included ± 1-1/2 LSB Maximum Conversion Time Total time to perform a single analog-to-digital conversion ML145050 ML145051 44 44 ADCLK cycles µs Data Transfer Time Total time to transfer digital serial data into and out of the device 10 to 16 SCLK cycles Sample Acquisition Time Analog input acquisition time window 6 SCLK cycles Minimum Total Cycle Time Total time to transfer serial data, sample the analog input, and perform the conversion ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz ML145051: SCLK = 2.1 MHz 26 49 µs Maximum Sample Rate Rate at which analog inputs may be sampled ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz ML145051: SCLK = 2.1 MHz 38 20.4 ks/s Issue B |
类似零件编号 - MC145050P |
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类似说明 - MC145050P |
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