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ML145053 数据表(PDF) 4 Page - LANSDALE Semiconductor Inc. |
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ML145053 数据表(HTML) 4 Page - LANSDALE Semiconductor Inc. |
4 / 15 page www.lansdale.com Page 4 of 15 Issue A ML145053 LANSDALE Semiconductor, Inc. AC ELECTRICAL CHARACTERISTICS (Full Temperature and Voltage Ranges per Operation Ranges Table) Figure Symbol Parameter Guaranteed Limit Unit 1 f Clock Frequency, SCLK (10-bit xfer) Min (11- to 16-bit xfer) Min Note: Refer to twH, twL below (10- to 16-bit xfer) Max) 0 Note 1 2.1 MHz 1 twH Minimum Clock High Time, SCLK 190 ns 1 twL Minimum Clock Low Time, SCLK 190 ns 1, 7 tPLH, tPHL Maximum Propagation Delay, SCLK to Dout 125 ns 1, 7 th Minimum Hold Time, SCLK to Dout 10 ns 2, 7 tPLZ, tPHZ Maximum Propagation Delay, CS to Dout High-Z 150 ns 2, 7 tPZL, tPZH Maximum Propagation Delay, CS to Dout Driven 2.3 µs 3 tsu Minimum Setup Time, Din to SCLK 100 ns 3 th Minimum Hold Time, SCLK to Din 0 ns 4, 7, 8 td Maximum Delay Time, EOC to Dout (MSB) 100 ns 5 tsu Minimum Setup Time, CS to SCLK 2.425 µs – tCSd Minimum Time Required Between 10th SCLK Falling Edge ( 0.8 V) and CS to Allow a Conversion Note 2 – tCAs Maximum Delay Between 10th SCLK Falling Edge ( 2 V) and CS to Abort a Conversion 9 µs 5 th Minimum Hold Time, Last SCLK to CS 0 ns 6, 8 tPHL Maximum Propagation Delay, 10th SCLK to EOC 2.35 µs 1 tr, tf Maximum Input Rise and Fall Times SCLK Din, CS 1 10 ms µs 1, 4, 6 – 8 tTLH, tTHL Maximum Output Transition Time, Any Output 300 ns – Cin Maximum Input Capacitance AN0 – AN4 SCLK, CS, Din 55 15 pF – Cout Maximum Three-State Output Capacitance Dout 15 pF NOTES: 1. After the 10th SCLK falling edge ( ≥ 2 V), at least 1 SCLK rising edge ( ≥ 2 V) must occur within 18.5 µs. 2. A CS edge may be received immediately after an active transition on the EOC pin. |
类似零件编号 - ML145053 |
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类似说明 - ML145053 |
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