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74VHC273SJ 数据表(PDF) 6 Page - Fairchild Semiconductor |
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74VHC273SJ 数据表(HTML) 6 Page - Fairchild Semiconductor |
6 / 13 page ©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC273 Rev. 1.5 6 AC Electrical Characteristics Notes: 3. Parameter guaranteed by design tOSLH = |tPLHmax – tPLHmin|; tOSHL = |tPHLmax – tPHLmin|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pieces of the Flip-Flop operates can be calculated by the equation: CPD (total) = 22 + 9n. AC Operating Requirements Note: 5. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V Symbol Parameter VCC (V) Conditions TA = 25°C TA = –40°C to +85°C Units Min. Typ. Max. Min. Max. fMAX Maximum Clock Frequency 3.3 ± 0.3 CL = 15pF 75 120 65 MHz CL = 50pF 50 75 45 5.0 ± 0.5 CL = 15pF 120 165 100 MHz CL = 50pF 80 110 70 tPLH, tPHL Propagation Delay Time (CK – Q) 3.3 ± 0.3 CL = 15pF 8.7 13.6 1.0 16.0 ns CL = 50pF 11.2 17.1 1.0 19.5 5.0 ± 0.5 CL = 15pF 5.8 9.0 1.0 10.5 ns CL = 50pF 7.3 11.0 1.0 12.5 tPHL Propagation Delay Time (MR – Q) 3.3 ± 0.3 CL = 15pF 8.9 13.6 1.0 16.0 ns CL = 50pF 11.4 17.1 1.0 19.5 5.0 ± 0.5 CL = 15pF 5.2 8.5 1.0 10.0 ns CL = 50pF 6.7 10.5 1.0 12.0 tOSLH, tOSHL Output to Output Skew 3.3 ± 0.3 (3) CL = 50pF 1.5 1.5 ns 5.0 ± 0.5 CL = 50pF 1.0 1.0 CIN Input Capacitance VCC = Open 4.0 10.0 10.0 pF CPD Power Dissipation Capacitance (4) 31 pF Symbol Parameter VCC (V) (5) TA = 25°C TA = –40°C to +85°C Units Typ. Guaranteed Minimum tW(L), tW(H) Minimum Pulse Width (CK) 3.3 5.5 6.5 ns 5.0 5.0 5.0 tW(L) Minimum Pulse Width (MR) 3.3 5.0 6.0 ns 5.0 5.0 5.0 tS Minimum Setup Time 3.3 5.5 6.5 ns 5.0 4.5 4.5 tH Minimum Hold Time 3.3 1.0 1.0 ns 5.0 1.0 1.0 tREC Minimum Removal Time (MR) 3.3 2.5 2.5 ns 5.0 2.0 2.0 |
类似零件编号 - 74VHC273SJ |
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类似说明 - 74VHC273SJ |
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