SN54HC590A, SN74HC590A

8BIT BINARY COUNTERS

WITH 3STATE OUTPUT REGISTERS

SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003

2

POST OFFICE BOX 655303

timing diagram

RCO

QA−QH

CCKEN

CCLR

OE

CCLK

COUNTER

(internal)

RCLK

Hex 01

Hex 02

Hex 03

Hex 04

Hex 05

Hex FD

Hex FE

Hex FF

Hex 00

Hex01

Hex 00

Hex 01

Hi-Z

Hex 01

Hex 05

Hex 00

TIMING SEQUENCE

1. Clear Counter (asynchronous).

2. Count up: 0x01. Store 0x00 in register.

3. Inhibit counter clock (CCKEN = HIGH). Store 0x01 in register.

4. Count 0x02, 0x03.

5. 3-state the outputs

6. Count up: 0x04

7. Enable outputs.

8. Continue up: 0x05

9. Store 0x05 in register.

10. Continue counting: 0x06...0xFD, 0xFE, 0xFF, 0x00, etc.

11. Store 0x00 in register.

Don’t

Care

Hex 00

Don’t

Care