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AD7147 数据表(PDF) 5 Page - Analog Devices |
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AD7147 数据表(HTML) 5 Page - Analog Devices |
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5 / 68 page  AD7147 Rev. 0 | Page 5 of 68 SPI TIMING SPECIFICATIONS (AD7147) TA = −40°C to +85°C, VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. Table 4. SPI Timing Specifications Parameter Limit Unit Description fSCLK 5 MHz max SCLK frequency t1 5 ns min CS falling edge to first SCLK falling edge t2 20 ns min SCLK high pulse width t3 20 ns min SCLK low pulse width t4 15 ns min SDI setup time t5 15 ns min SDI hold time t6 20 ns max SDO access time after SCLK falling edge t7 16 ns max CS rising edge to SDO high impedance t8 15 ns min SCLK rising edge to CS high CS SCLK SDI SDO t1 116 15 MSB LSB 23 MSB LSB 12 15 16 t2 t4 t5 t3 t6 t7 t8 Figure 2. SPI Detailed Timing Diagram |
类似零件编号 - AD7147 |
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类似说明 - AD7147 |
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