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CAT25C64LI-GT3 数据表(PDF) 4 Page - Catalyst Semiconductor |
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CAT25C64LI-GT3 数据表(HTML) 4 Page - Catalyst Semiconductor |
4 / 16 page 4 CAT25C64 Doc. No. 1112, Rev. B © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice FUNCTIONAL DESCRIPTION The CAT25C64 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C64 to interface directly with many of today’s popular microcontrollers. The CAT25C64 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. PIN DESCRIPTION SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C64. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C64. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory INSTRUCTION SET Figure 1. Sychronous Data Timing Note: Dashed Line= mode (1, 1) — ——— VALID IN VIH VIL tCSS VIH VIL VIH VIL VOH VOL HI-Z tSU tH tWH tWL tV tCS tCSH tHO tDIS HI-Z CS SCK SI SO tRI tFI |
类似零件编号 - CAT25C64LI-GT3 |
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类似说明 - CAT25C64LI-GT3 |
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