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CAT25C64PI-GT3 数据表(PDF) 9 Page - Catalyst Semiconductor |
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CAT25C64PI-GT3 数据表(HTML) 9 Page - Catalyst Semiconductor |
9 / 16 page 9 CAT25C64 Doc. No. 1112, Rev. B © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CS SCK HOLD SO tCD tHD tHD tCD tLZ tHZ HIGH IMPEDANCE Figure 9. HOLD HOLD HOLD HOLD HOLD Timing Figure 8. Page Write Instruction Timing Note: Dashed Line = mode (1, 1) – – – – Note: Dashed Line= mode (1, 1) — — — — SCK SI SO 0 0 0 0 0 0 1 0 ADDRESS Data Byte 1 012345678 21 22 23 24-31 32-39 Data Byte 2 Data Byte 3 Data Byte N CS OPCODE 7..1 0 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1 DATA IN HIGH IMPEDANCE state and receive an instruction. After a successful byte/ page write or status register write the CAT25C64 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and program-ming is continued. On power up, SO is in a high impedance. When powering down, the supply should be taken down to 0V, so that the CAT25C64 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT25C64 can be reset by refreshing the contents of the Status Register (See Application Note AN10). tCSH CS SCK WP WP tWPS tWPH Figure 10. WP WP WP WP WP Timing Note: Dashed Line= mode (1, 1) — — — — |
类似零件编号 - CAT25C64PI-GT3 |
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类似说明 - CAT25C64PI-GT3 |
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