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CAT24WC05JE-1.8TE13 数据表(PDF) 5 Page - Catalyst Semiconductor

部件名 CAT24WC05JE-1.8TE13
功能描述  2K/4K-Bit Serial EEPROM with Partial Array Write Protection
Download  14 Pages
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制造商  CATALYST [Catalyst Semiconductor]
网页  http://www.catalyst-semiconductor.com
标志 CATALYST - Catalyst Semiconductor

CAT24WC05JE-1.8TE13 数据表(HTML) 5 Page - Catalyst Semiconductor

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Discontinued
Parts
CAT24WC03/05
5
Doc. No. 1005, Rev. F
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A total of four devices can be addressed on a single bus
when using the CAT24WC05 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to VSS or left
floating. If only one CAT24WC05 is being addressed on
the bus, the address pins (A1 and A2) can be left floating
or connected to VSS.
WP: Write Protect
If the WP pin is tied to VCC the upper half of memory array
becomes Write Protected (READ only)(locations 80H to
FFH for the CAT24WC03 and locations 100H to 1FFH
for the CAT24WC05). When the WP pin is tied to VSS or
left floating normal read/write operations are allowed to
the device.
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05 monitor
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC03/05 (see Fig. 5). The next
three significant bits (A2, A1, A0) are the device address
bits and define which device or which part of the device
the Master is accessing. Up to eight CAT24WC03 and
four CAT24WC05 can be individually addressed by the
system.
The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC03/05 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC03/05 then performs a Read or Write operation
depending on the state of the R/
W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
ACKNOWLEDGE
1
START
SCL FROM
MASTER
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8 corresponds to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
1
0
1
0
A2
A1
A0
R/W
1
0
1
0
A2
A1
a8
R/W
24WC03
24WC05


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