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SN74ACT8990 数据表(PDF) 8 Page - Texas Instruments |
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SN74ACT8990 数据表(HTML) 8 Page - Texas Instruments |
8 / 15 page SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES SCAS190E – JUNE 1990 – REVISED JANUARY 1997 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 1) SN54ACT8990 SN74ACT8990 UNIT MIN MAX MIN MAX UNIT fclock Clock frequency 0 30 0 30 MHz RD low† 5.5 ns WR low 5.5 5.5 tw Pulse duration EVENT high or low 8 8 ns TCKI high or low 10.5 10.5 ns TRST low 6 6 ADRS† before RD ↑ 6.5 ns ADRS before WR ↑ 6.5 6.5 DATA before WR ↑ 6 6 tsu Setup time EVENT before TCKI ↑ 6 5.5 ns EVENT before TCKI ↓ 5 5 ns TDI before TCKI ↑ 2 2 TDI before TCKI ↓ 2 2 ADRS† after RD ↑ 5 ns ADRS after WR ↑ 5.5 5 DATA after WR ↑ 5.5 5.5 th Hold time EVENT after TCKI ↑ 5.5 5 ns EVENT after TCKI ↓ 5 5 ns TDI after TCKI ↑ 4 2.5 TDI after TCKI ↓ 4 2.5 † Applies only in the case where ADRS (4-0) = 10110 (read buffer). |
类似零件编号 - SN74ACT8990 |
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类似说明 - SN74ACT8990 |
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