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SI5366 数据表(PDF) 7 Page - Silicon Laboratories |
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SI5366 数据表(HTML) 7 Page - Silicon Laboratories |
7 / 20 page Si5366 Preliminary Rev. 0.2 7 2. Pin Descriptions: Si5366 Table 3. Si5366 Pin Descriptions Pin # Pin Name I/O Signal Level Description 1, 2, 23, 24, 25, 32, 47, 48, 52, 53, 72, 73, 74, 75, 90 NC No Connect. These pins must be left unconnected for normal operation. 3RST ILVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. After rising edge of RST signal, the device will perform an internal self-calibration. This pin has a weak pull-up. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49 AUTOSEL NC FS_SW FS_ALIGN C2B GND C1B C3B ALRMOUT XA XB VDD CK_CONF FRQSEL3 DIV34_1 DIV34_0 FRQSEL1 FRQSEL0 GND VDD BWSEL1 BWSEL0 C2A C1A CS1_C4A FOS_CTL DEC INC 17 20 19 18 24 23 22 21 25 74 73 72 71 70 69 68 67 66 65 75 100 89 90 91 92 93 94 95 96 97 98 99 76 77 78 79 80 81 82 83 84 85 86 87 88 RST FRQTBL NC VDD GND CS0_C3A GND GND GND NC NC NC VDD FRQSEL2 GND NC NC NC NC NC NC VDD Si5366 GND PAD |
类似零件编号 - SI5366 |
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类似说明 - SI5366 |
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