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SI533KA00100DGR 数据表(PDF) 4 Page - Silicon Laboratories |
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SI533KA00100DGR 数据表(HTML) 4 Page - Silicon Laboratories |
4 / 12 page Si533 4 Rev. 1.1 Table 4. CLK± Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS)* for FOUT > 500 MHz φ J 12 kHz to 20 MHz (OC-48) — 0.25 0.40 ps 50 kHz to 80 MHz (OC-192) — 0.26 0.37 Phase Jitter (RMS)* for FOUT of 125 to 500 MHz φ J 12 kHz to 20 MHz (OC-48) — 0.36 0.50 ps 50 kHz to 20 MHz (OC-192) — 0.34 0.42 *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. Table 5. CLK± Output Period Jitter Parameter Symbol Test Condition Min Typ Max Units Period Jitter* JPER RMS — 2 — ps Peak-to-Peak — 14 — *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Table 6. CLK± Output Phase Noise (Typical) Offset Frequency (f) 120.00 MHz LVDS 156.25 MHz LVPECL 622.08 MHz LVPECL Units 100 Hz 1kHz 10 kHz 100 kHz 1MHz 10 MHz 100 MHz –112 –122 –132 –137 –144 –150 n/a –105 –122 –128 –135 –144 –147 n/a –97 –107 –116 –121 –134 –146 –148 dBc/Hz |
类似零件编号 - SI533KA00100DGR |
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类似说明 - SI533KA00100DGR |
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