10

COMMERCIALTEMPERATURERANGE

IDTAMB0480

ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM

PIN DESCRIPTION

Signal

Type

Description

Channel Interface

PN[13:0]

O

Northbound Output Data: High speed serial signal. Read path from AMB toward host on primary side of the DIMM connector.

PN[13:0]

O

Northbound Output Data Complement

SN[13:0]

I

Northbound Input Data: High speed serial signal. Read path from the previous AMB toward this AMB on secondary side of the DIMM

connector.

SN[13:0]

I

Northbound Input Data Complement

PS[9:0]

I

Southbound Input Data: High speed serial signal. Write path from host toward AMB on primary side of the DIMM connector.

PS[9:0]

I

Southbound Input Data Complement

SS[9:0]

O

Southbound Output Data: High speed serial signal. Write path from this AMB toward next AMB on secondary side of the DIMM connector.

These output buffers are disabled for the last AMB on the channel.

SS[9:0]

O

Southbound Output Data Complement

FBDRES

A

External 100

DRAM Interface

CB[7:0]

I/O

Check bits

DQ[63:0]

I/O

Data

DQS[17:0]

I/O

Data Strobe: DDR2 data and check-bit strobe.

DQS[17:0]

I/O

Data Strobe Complement: DDR2 data and check-bit strobe complements.

A0A-A15A,

O

Address: Used for providing multiplexed row and column address to SDRAM.

A0B-A15B

BA0A-BA2A,

O

Bank Active: Used to select the bank within a rank.

BA0B-BA2B

RASA, RASB

O

Row Address Strobe: Used with

CS, CAS, and WE to specify the SDRAM command.

CASA, CASB

O

Column Address Strobe: Used with

CS, RAS, and WE to specify the SDRAM command.

WEA, WEB

O

Write Enable: Used with

CS, CAS, and RAS to specify the SDRAM command.

CS0A-CS1A,

O

Chip Select: Used with

CAS, RAS, and WE to specify the SDRAM command. These signals are used for selecting one of two SDRAM

ranks.

CS0 is used to select the first rank and CS1 is used to select the second rank.

CKE0A-CKE1A,

O

Clock Enable: DIMM command register enable.

CKE0B-CKE1B

ODT0A, ODT0B

O

DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel.

CLK[3:0]

O

Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are used when the AMB is configured for dual rank DIMMs.

CLK[3:0]

O

Clock Complement: Clocks to DRAMs.

DDR Compensation

DDRC_C14

A

DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18

DDRC_B18

A

DDR Compensation Ball Resistor (825

Ω)connectedtoCompensationCommonabove

DDRC_C18

A

DDR Compensation Ball Resistor (121

Ω)connectedtoCompensationCommonabove

DDRC_B12

A

DDR Compensation Ball Resistor (82

DDRC_C12

A

DDR Compensation Ball Resistor (82

CS0B-CS1B