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CS8416 数据表(PDF) 5 Page - Cirrus Logic |
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CS8416 数据表(HTML) 5 Page - Cirrus Logic |
5 / 60 page DS578F3 5 CS8416 LIST OF FIGURES Figure 1. Audio Port Master Mode Timing ................................................................................................... 9 Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 9 Figure 3. SPI Mode Timing ........................................................................................................................ 10 Figure 4. I²C Mode Timing ......................................................................................................................... 11 Figure 5. Typical Connection Diagram - Software Mode ........................................................................... 20 Figure 6. Typical Connection Diagram - Hardware Mode .......................................................................... 21 Figure 7. Serial Audio Output Example Formats........................................................................................ 24 Figure 8. AES3 Data Format...................................................................................................................... 25 Figure 9. Receiver Input Structure ............................................................................................................. 27 Figure 10. C/U Data Outputs...................................................................................................................... 32 Figure 11. Control Port Timing in SPI Mode .............................................................................................. 33 Figure 12. Control Port Timing, I²C Slave Mode Write............................................................................... 34 Figure 13. Control Port Timing, I²C Slave Mode Read............................................................................... 34 Figure 14. De-Emphasis Filter Response .................................................................................................. 39 Figure 15. Hardware Mode Data Flow ....................................................................................................... 46 Figure 16. Professional Input Circuit .......................................................................................................... 49 Figure 17. Transformerless Professional Input Circuit ............................................................................... 49 Figure 18. Consumer Input Circuit ............................................................................................................. 50 Figure 19. S/PDIF MUX Input Circuit ......................................................................................................... 50 Figure 20. TTL/CMOS Input Circuit............................................................................................................ 50 Figure 21. Channel Status Data Buffer Structure....................................................................................... 52 Figure 22. Flowchart for Reading the E Buffer........................................................................................... 52 Figure 23. PLL Block Diagram ................................................................................................................... 53 Figure 24. Recommended Layout Example............................................................................................... 54 Figure 25. Jitter Attenuation Characteristics of PLL................................................................................... 55 LIST OF TABLES Table 1. Typical Delays by Frequency Values ........................................................................................... 26 Table 2. Clock Switching Output Clock Rates............................................................................................ 28 Table 3. GPO Pin Configurations............................................................................................................... 29 Table 4. Hardware Mode Start-Up Pin Conditions ..................................................................................... 47 Table 5. Hardware Mode Serial Audio Format Select................................................................................ 48 Table 6. External PLL Component Values ................................................................................................. 54 |
类似零件编号 - CS8416_07 |
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类似说明 - CS8416_07 |
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