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TSA5060ATS 数据表(PDF) 6 Page - NXP Semiconductors |
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TSA5060ATS 数据表(HTML) 6 Page - NXP Semiconductors |
6 / 24 page 2000 Oct 24 6 Philips Semiconductors Product specification 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer TSA5060A The TSA5060A is controlled via the two-wire I2C-bus. For programming, there is one 7-bit module address and bit R/W for selecting READ or WRITE mode. To be able to have more than one synthesizer in an I2C-bus system, one of four possible addresses is selected depending on the voltage applied at pin AS (see Table 3). The TSA5060A fulfils the fast mode I2C-bus, according to the Philips I2C-bus specification. The I2C-bus interface is designed in such a way that pins SCL and SDA can be connected either to 5 or 3.3 V pulled-up I2C-bus lines, allowing the PLL synthesizer to be connected directly to the bus lines of a 3.3 V microcontroller. WRITE mode: R/W=0 After the address transmission (first byte), data bytes can be sent to the device (see Table 1). Four data bytes are needed to fully program the TSA5060A. The bus transceiver has an auto-increment facility that permits programming of the TSA5060A within one single transmission (address + 4 data bytes). The TSA5060A can also be partly programmed on the condition that the first data byte following the address is byte 2 or 4. The meaning of the bits in the data bytes is given in Table 1. The first bit of the first data byte indicates whether byte 2 (first bit is logic 0) or byte 4 (first bit is logic 1) will follow. Until an I2C-bus STOP condition is sent by the controller, additional data bytes can be entered without the need to re-address the device. To allow a smooth frequency sweep for fine tuning, and while the data of the dividing ratio of the main divider is in data bytes 2, 3 and 4, it is necessary to change the frequency to send the data bytes 2 to 5 in a repeated sending, or to finish an incomplete transmission by a STOP condition. Repeated sending of data bytes 2 and 3 without ending the transmission does not change the dividing ratio. To illustrate, the following data sequences will change the dividing ratio: • Bytes 2, 3, 4 and 5 • Bytes 4, 5, 2 and 3 • Bytes 2, 3, 4 and STOP • Bytes 4, 5, 2 and STOP • Bytes 2, 3 and STOP • Bytes 2 and STOP • Bytes 4 and STOP. Table 1 Write data format Note 1. MSB is transmitted first. BYTE DESCRIPTION MSB(1) LSB CONTROL BIT 1 address 1 1 0 0 0 MA1 MA0 0 A 2 programmable divider 0 N14 N13 N12 N11 N10 N9 N8 A 3 programmable divider N7 N6 N5 N4 N3 N2 N1 N0 A 4 control data 1 N16 N15 PE R3 R2 R1 R0 A 5 control data C1 C0 XCE XCS P3 P2/T2 P1/T1 P0/T0 A |
类似零件编号 - TSA5060ATS |
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类似说明 - TSA5060ATS |
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