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SN74ALVCH16373GRDR 数据表(PDF) 3 Page - Texas Instruments |
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SN74ALVCH16373GRDR 数据表(HTML) 3 Page - Texas Instruments |
3 / 19 page www.ti.com 1OE 1LE 1D1 To Seven Other Channels 1Q1 2OE 2LE 2D1 2Q1 To Seven Other Channels 1 48 47 24 25 36 C1 1D 13 2 C1 1D Pin numbers shown are for the DGG and DL packages. Absolute Maximum Ratings (1) SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020I – JULY 1995 – REVISED NOVEMBER 2005 FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OUTPUT Q OE LE D L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 4.6 V VI Input voltage range(2)(3) –0.5 VCC + 0.5 V VO Output voltage range(2)(3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current ±50 mA Continuous current through each VCC or GND ±100 mA DGG package 70 DL package 63 θ JA Package thermal impedance(4) °C/W GQL/ZQL package 42 GRD/ZRD package 36 Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) This value is limited to 4.6 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7. 3 |
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