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TDA4885 数据表(PDF) 11 Page - NXP Semiconductors |
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TDA4885 数据表(HTML) 11 Page - NXP Semiconductors |
11 / 56 page 1997 Nov 25 11 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 10 CHARACTERISTICS All voltages and currents are measured in test circuit of Fig.19; all voltages are measured with respect to GND (pins 9, 28, 23 and 18); VP =VP1, 2, 3 = 8 V (pins 7, 29, 24 and 19); Tamb =25 °C; nominal input signals [0.7 V (peak-to-peak value) at pins 6, 8 and 10]; nominal colour signals at signal outputs (pins 30, 25 and 20); reference black level (Vrbl) approximately 0.7 V; nominal settings for brightness and contrast; maximum settings for OSD contrast and gain; no limiting of contrast (V17 = 5 V); no OSD fast blanking (pin 1 connected to ground); no gain modulation (pins 12, 13 and 14 connected to ground); notes 1 to 3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage (pin 7) 7.6 8.0 8.8 V IP supply current (pin 7) note 4 − 20 25 mA VP1, 2, 3 channel supply voltage (pins 29, 24 and 19) 7.6 8.0 8.8 V IP1, 2, 3 channel supply current (pins 29, 24 and 19) signal outputs (pins 30, 25 and 20) open-circuit; Vrbl = 0.7 V; note 5 − 40 45 mA VPSO supply voltage for signal switch off (threshold at pin 7) signal outputs switched to switch-off voltage; note 1 −− 7.2 V Clamping and blanking pulses (pins 5 and 11) V5 input clamping and vertical blanking input signal note 6 no blanking, no input clamping −0.1 − +1.2 V blanking, no input clamping 1.6 − 2.6 V input clamping, no blanking 3.5 − VP V I5 input current V5 = 1 V; note 7 −1.5 −0.2 −0.05 µA pin 5 grounded; note 7 −80 −60 −30 µA V5 = −0.1 V; note 7 −250 −200 −100 µA tr/f5 rise/fall time for input clamping pulse, disable for blanking note 6; see Fig.7 −− 75 ns/V tW5 width of input clamping pulse 0.6 −− µs tdl5 delay between leading edges of vertical blanking input pulse and internal blanking pulse V11 < 0.8 V; input pulse with 50 ns/V; threshold for rising input pulse V5 = 1.4 V; threshold after input clamping pulse V5 = 3 V; see Fig.7 − 270 − ns tdt5 delay between trailing edges of vertical blanking input pulse and internal blanking pulse V11 < 0.8 V; input pulse with 50 ns/V; threshold V5 = 1.4 V; see Fig.7 − 115 − ns V11 output clamping and blanking input signal note 8 no blanking, no output clamping −0.1 − +0.8 V blanking, no output clamping 2.0 − 2.6 V blanking, output clamping 3.5 − VP V |
类似零件编号 - TDA4885 |
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类似说明 - TDA4885 |
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