TDA4671 datasheet(8/16 Pages) PHILIPS

部件名	TDA4671

功能描述	Picture Signal Improvement PSI circuit

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制造商	PHILIPS [NXP Semiconductors]

网页	http://www.nxp.com

标志

8 / 16 page

1996 Dec 11

8

Philips Semiconductors

Product speciﬁcation

Picture Signal Improvement (PSI) circuit

TDA4671

Colour-difference paths measured with transient times tr =tf =1 µs; tp H ≥ 1 µs; Vi = 1.33 V (p-p) on

pins 3 and 7 and with burst key pulse tBK =4 µs

Vi(CD)(p-p)

±(R − Y) input signal

(peak-to-peak value; pin 3)

75% colour bar

−

1.05

1.48

V

±(B − Y) input signal

(peak-to-peak value; pin 7)

75% colour bar

−

1.33

1.88

V

input transient sensitivity

V3,7/δt

0.22

−−

V/

µs

V3,7

internal clamping voltage level

−

2.45

−

V

I3,7

input current

outside clamping

−−±1

µA

during clamping

±100

−±190

µA

C3,7

input capacitance

−

612

pF

V4,6

DC output voltage

−

2

−

V

∆V4,6

output offset voltage

RS ≤ 300 Ω; note 1

−−±5mV

during and after storage time

−−±18

mV

Vspike

spurious spike signals on pins 4

and 6

RS ≤ 300 Ω; note 1

−−±30

mV

I4,6

output current (emitter-follower with

constant current source)

source current

−1

−−

mA

sink current

0.4

−−

mA

R4,6

output resistance

−−

100

Ω

Gv

signal gain in each path

Vo/Vi

−1

0

+1

dB

∆Gv

gain difference

−(R − Y)/−(B − Y)

−

0

±0.3

dB

LIN

signal linearity for

αmin/αmax;

nominal signal

Vi = 1.33 V (p-p)

0.90

−−−

+3 dB signal

Vi = 1.88 V (p-p)

0.65

−−−

∆Vo

signal reduction at higher frequency

(output signal ratio Vi/Vo)

signal with tp H = 50 ns;

tr =tf =1 µs

−1.5

−−

dB

Sandcastle pulse, input voltage selectable via I2C-bus

V17

input voltage threshold for H and V

sync

SC5-bit = 0 (12 V)

1.1

1.5

1.9

V

input voltage threshold for burst

SC5-bit = 0 (12 V)

5.5

6.5

7.5

V

input voltage threshold for H and V

sync

SC5-bit = 1 (5 V)

1.1

1.5

1.9

V

input voltage threshold for burst

SC5-bit = 1 (5 V)

3.0

3.5

4.0

V

R17

input resistance

+12 V input level

30

40

50

k

Ω

+5 V input level

15

20

25

k

Ω

C17

input capacitance

−

48pF

tBK

burst key pulse width

3.0

4.0

4.6

µs

td

leading edge delay for clamping

pulse

referred to tBK

−

1

−µs

np

number of required burst key pulses

vertical blanking interval

note 2

4

−

31

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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