2001 Oct 01

2

Philips Semiconductors

Product specification

DVB-C channel receiver

TDA10021HT

FEATURES

• 4, 16, 32, 64, 128 and 256 Quadrature Amplitude

Modulation (QAM) demodulator (DVB-C compatible:

ETS 300-429/ITU-T J83 annex A/C)

• High performance for 256 QAM, especially for direct

IF applications

• On-chip 10-bit Analog-to-Digital Converter (ADC)

• On-chip Phase-Locked Loop (PLL) for crystal frequency

multiplication (typically 4 MHz crystal)

• Digital downconversion

• Programmable half Nyquist filter (roll off = 0.15 or 0.13)

• Two Pulse Width Modulated (PWM) AGC outputs with

programmable take over point (for tuner and

downconverter control)

• Clock timing recovery, with programmable 2nd-order

loop filter

• Variable symbol rate capability from SACLK/64 to

SACLK/4 (SACLK = 36 MHz maximum)

• Programmable anti-aliasing filters

• Full digital carrier recovery loop

• Carrier acquisition range up to 18% of symbol rate

• Integrated adaptive equalizer (linear transversal

equalizer or decision feedback equalizer)

• On-chip Forward Error Correction (FEC) decoder

(de-interleaver and RS decoder) and fully DVB-C

compliant

• DVB compatible differential decoding and mapping

• Parallel and serial transport stream interface

simultaneously

• CMOS 0.2 µm technology.

APPLICATIONS

• Cable set-top boxes

• Cable modems

• MMDS (ETS 300-749) set-top boxes.

GENERAL DESCRIPTION

The TDA10021HT is a single-chip DVB-C channel

receiver for 4, 16, 32, 64, 128 and 256 QAM modulated

signals. The device interfaces directly to the IF signal,

which is sampled by a 10-bit ADC.

The TDA10021HT performs the clock and the carrier

recovery functions. The digital loop filters for both clock

and carrier recovery are programmable in order to

optimize their characteristics according to the current

application.

After baseband conversion, equalization filters are used

for echo cancellation in cable applications. These filters

are configured as either a T-spaced transversal equalizer

or a Decision Feedback Equalizer (DFE), so that the

system performance can be optimized according to the

network characteristics. A proprietary equalization

algorithm, independent of carrier offset, is achieved in

order to assist carrier recovery. A decision directed

algorithm then takes place, to achieve final equalization

convergence.

The TDA10021HT implements a FORNEY convolutional

de-interleaver of depth 12 blocks and a Reed-Solomon

decoder which corrects up to 8 erroneous bytes. The

de-interleaver and the RS decoder are automatically

synchronized by the frame synchronization algorithm

which uses the MPEG-2 sync byte. Finally descrambling

according to DVB-C standard, is achieved at the Reed

Designed in 0.2

µm CMOS technology and housed in a

64 pin TQFP package, the TDA10021HT operates over

the commercial temperature range.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA10021HT

TQFP64

plastic thin quad flat package; 64 leads; body 10

× 10 × 1.0 mm

SOT357-1