数据搜索系统,热门电子元器件搜索 |
|
SA1638BE 数据表(PDF) 10 Page - NXP Semiconductors |
|
SA1638BE 数据表(HTML) 10 Page - NXP Semiconductors |
10 / 26 page Philips Semiconductors Product specification SA1638 Low voltage IF I/Q transceiver 1997 Sept 03 10 The overall filter response in the receive section is the sum of the filter responses of the passive RC low-pass filter and the active gyrator filter. Power Down Modes There are 4 power-on pins in the SA1638: PON, PONRx, PDTx, PONPLL. PON = H powers up both voltage regulators VREG1 and VREG2. PON should be set to L, if these internal voltage regulators are not to be used. PONRx = H powers up the receiver part. PDTx = L powers up the transmitter part. PONPLL = H powers up the synthesizer part. As it also powers up the first divide by 2 stage for generating the 0/90 degree phase shifted signals for the transmit and receive mixers, it also has to be set H if either the transmit part or the receive part is used. PONPLL = L powers down the dividers, resets the phase detector and disconnects the current setting pin IREF. In PONPLL = L mode, the values in the serial input registers are still kept and the part still can be reprogrammed as long as VCCDIG is present. Table 3. Definition of SA1638 Serial Registers First data word: (shown with default values) Address SA1638 Sub Adr N-Divider Ref ÷ Reg Charge-Pump Reg Test MSB LSB a0 a1 a2 a3 sa n0 n1 n2 n3 n4 n5 n6 n7 n8 r0 r1 c0 c1 c2 x0 x1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 Address: 4 bits, a0...a3, fixed to 1110 Sub:Address: 1 bit, sa, fixed to 0 for first data word N-Divider: 9 bits, n0...n8, values 64 (00100 0000) to 511 (111111111) allowed for IF-choice, default 400 Reference Divider Register: 2 bits, r0...r1, 00 = ÷13, 01 = ÷26, 10 = ÷39, 11 = ÷52. Default: 00 Charge-Pump Register: 3 bits, c0...c2, Binary current setting factor for charge pumps, values 000 = minimum current to 111 = maximum current, default maximum charge pump current Test Register: 2 bits, x0...x1, default 00, see Functional Description Second data word: (shown with default values) Address SA1638 Sub Status DC Offset Register Mode Select Register Address SA1638 Adr Reg Q-Channel I-Channel Mode Select Register MSB LSB a0 a1 a2 a3 sa s0 s1 q0 q1 q2 q3 i0 i1 i2 i3 t0 t1 t2 t3 t4 t5 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address: 4 bits, a0...a3, fixed to 1110 Sub:Address: 1 bit, sa, fixed to 1 for second data word Status Register: 2 bits, s0 sets pin AOUT; s1 sets pin BOUT, see Functional Description DC Offset Register: 4 bits per channel, i0...i3 and q0...q3, no correction as default i0 and q0 switches offset polarity, 0 to lower voltage, 1 to higher voltage il...i3 and q1...q3, 000 no correction to 111 max. correction enabled Mode Select Register: 6 bits, t0...t5, 000000 = normal GSM-Operation as default, see Functional Description |
类似零件编号 - SA1638BE |
|
类似说明 - SA1638BE |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |