Quad Voltage Monitor and Sequencer

ADM1185

Rev. 0

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FEATURES

Powered from 2.7 V to 5.5 V on the VCC pin

Monitors 4 supplies via 0.8% accurate comparators

Logical core with internal timeouts provides power supply

sequencing and fault protection

4 inputs can be programmed to monitor different voltage

levels with resistor dividers

3 open-drain enable outputs

Open-drain power-good output (PWRGD)

10-lead MSOP

APPLICATIONS

Monitor and alarm functions

Power supply sequencing

Telecommunication and data communication equipment

PC/servers

FUNCTIONAL BLOCK DIAGRAM

VIN1

REF = 0.6V

OUT1

VIN2

REF = 0.6V

OUT2

VIN3

REF = 0.6V

OUT3

VIN4

REF = 0.6V

PWRGD

GND

POWER AND

REFERENCE

GENERATOR

REF = 0.6V

STATE

MACHINE

CORE

VCC

ADM1185

Figure 1.

GENERAL DESCRIPTION

The ADM1185 is an integrated, four-channel, voltage

monitoring and sequencing device. A 2.7 V to 5.5 V power

supply is required on the VCC pin to power the device.

Four precision comparators monitor four voltage rails.

All comparators have a 0.6 V reference with a worst-case

accuracy of 0.8%. Resistor networks that are external to the

VIN1, VIN2, VIN3, and VIN4 pins set the trip points for

the monitored supply rails.

A digital core interprets the status of the comparator outputs.

Internal time delays can be used for sequencing the startup of

subsequent power supplies enabled by the outputs. Supplies

falling out of range are also detected and, as a result, appropriate

outputs are disabled.

The ADM1185 has four open-drain outputs. In a typical

configuration, OUT1 to OUT3 are used to enable power

supplies, while PWRGD is a common power-good output

indicating the status of all monitored supplies.

The ADM1185 is available in a 10-lead mini small outline

package (MSOP).

APPLICATIONS DIAGRAM

2.5V OUT

3.3V IN

1.8V OUT

1.2V OUT

2.5V OUT

1.8V OUT

1.2V OUT

OUT1

VIN1

OUT2

VIN2

OUT3

VIN3

VIN4

GND

PWRGD

POWER

GOOD

VCC

ADM1185

GND

REGULATOR1

IN

EN

OUT

GND

REGULATOR2

IN

EN

OUT

GND

REGULATOR3

IN

EN

OUT

Figure 2.