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AD7764 数据表(PDF) 10 Page - Analog Devices |
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AD7764 数据表(HTML) 10 Page - Analog Devices |
10 / 32 page AD7764 Rev. 0 | Page 10 of 32 Pin No. Mnemonic Description 14 FSI Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first data bit is latched in on the next SCO falling edge. See the AD7764 Interface section for further details. 15 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. See the Synchronization section for further details. 16 RESET/ PWRDWN Reset/Power-down Pin. When a logic low is sensed on this pin, the part is powered down and all internal circuitry is reset. 19 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the Clocking the AD7764 section for more details. 18 DEC_RATE Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a decimation rate 64× is selected. A decimation rate of 128× is selected by leaving the pin floating. A decimation rate of 256× is selected by setting the pin to ground. |
类似零件编号 - AD7764_07 |
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类似说明 - AD7764_07 |
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