74AC11239

DUAL 2–LINE TO 4–LINE DECODER/DEMULTIPLEXER

SCAS072A – JULY 1989 – REVISED APRIL 1993

2

POST OFFICE BOX 655303

POST OFFICE BOX 1443

DMUX

0

1

G

0

3

1A

1B

1G

2A

2B

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

2G

15

14

13

10

9

11

16

1

2

3

5

6

7

8

X/Y

0

1

1A

1B

1G

2A

2B

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

2G

15

14

13

10

9

11

16

1

2

3

5

6

7

8

EN

0

1

2

3

0

1

2

3

† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

2Y3

2Y2

2Y1

2Y0

1Y3

1Y2

1Y1

1Y0

8

7

6

5

3

2

1

16

13

15

14

1A

1B

11

10

9

Enable 1G

Enable 2G

2A

2B

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Data Outputs