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ATMEGA325P 数据表(PDF) 99 Page - ATMEL Corporation |
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ATMEGA325P 数据表(HTML) 99 Page - ATMEL Corporation |
99 / 336 page 99 8023A–AVR–12/06 ATmega325P/3250P Figure 13-7. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 13-5 on page 104). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 13-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOT- TOM. There are two cases that give a transition without Compare Match. • OCR0A changes its value from MAX, like in Figure 13-7. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure TOVn Interrupt Flag Set OCnx Interrupt Flag Set 1 2 3 TCNTn Period OCn OCn (COMnx1:0 = 2) (COMnx1:0 = 3) OCRnx Update f OCnxPCPWM f clk_I/O N 510 ⋅ ------------------ = |
类似零件编号 - ATMEGA325P_06 |
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类似说明 - ATMEGA325P_06 |
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