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ISL51002EVALZ 数据表(PDF) 6 Page - Intersil Corporation |
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ISL51002EVALZ 数据表(HTML) 6 Page - Intersil Corporation |
6 / 32 page 6 December 22, 2006 Timing Diagrams Data Output Setup and Hold Timing RGB Output Data Timing and Latency YUV Output Data Timing and Latency PIXEL DATA DATACLK tHOLD tSETUP DATACLK PROGRAMMABLE WIDTH AND POLARITY ANALOG VIDEO IN P1 P2 P3 P4 P5 P6 P7 P8 P0 P9 D0 R/G/B[9:0] HSOUT 8 DATACLK PIPELINE LATENCY P10 P11 P12 D1 D2 D3 HSYNCIN THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE AFE’S OUTPUT SIGNALS DATACLK PROGRAM MABLE W IDTH AND POLARITY ANALOG VIDEO IN P1 P2 P3 P4 P5 P6 P7 P8 P0 P9 HSOUT 8 DATACLK PIPELINE LATENCY P10 P11 P12 HSYNCIN THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO. THE SAM PLING PHASE SETTING DETERM INES ITS RELATIVE POSITION TO THE REST OF THE AFE’S OUTPUT SIGNALS DATACLK G0 (YO) G1 (Y1)G2 (Y2) B0 (UO)R0 (V0)B2 (U2) G[9:0] R[9:0] B[9:0] G3 (Y3) R2 (V2) ISL51002 |
类似零件编号 - ISL51002EVALZ |
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类似说明 - ISL51002EVALZ |
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