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DM74ALS652 数据表(PDF) 4 Page - Fairchild Semiconductor |
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DM74ALS652 数据表(HTML) 4 Page - Fairchild Semiconductor |
4 / 6 page www.fairchildsemi.com 4 Switching Characteristics over recommended operating free air temperature range (Note 6) Note 6: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. Symbol Parameter Conditions From (Input) Min Max Units To (Output) tPLH Propagation Delay Time VCC = 4.5V to 5.5V, CBA or CAB 10 30 ns LOW-to-HIGH Level Output CL = 50 pF, to A or B tPHL Propagation Delay Time R1 = R2 = 500Ω,CBA or CAB 517 ns HIGH-to-LOW Level Output TA = Min to Max to A or B tPLH Propagation Delay Time A or B to 518 ns LOW-to-HIGH Level Output B or A tPHL Propagation Delay Time A or B to 312 ns HIGH-to-LOW Level Output B or A tPLH Propagation Delay Time LOW-to-HIGH Level Output SBA or SAB 12 35 ns (with A or B LOW) (Note 6) to A or B tPHL Propagation Delay Time HIGH-to-LOW Level Output SBA or SAB 6 20 ns (with A or B LOW) (Note 6) to A or B tPLH Propagation Delay Time LOW-to-HIGH Level Output SBA or SAB 6 25 ns (with A or B HIGH) (Note 6) to A or B tPHL Propagation Delay Time HIGH-to-LOW Level Output SBA or SAB 5 20 ns (with A or B HIGH) (Note 6) to A or B tPZH Output Enable Time GBA to 317 ns to HIGH Level Output A tPZL Output Enable Time GBA to 518 ns to LOW Level Output A tPHZ Output Disable Time GBA to 110 ns from HIGH Level Output A tPLZ Output Disable Time GBA to 216 ns from LOW Level Output A tPZH Output Enable Time GAB to 622 ns to HIGH Level Output B tPZL Output Enable Time GAB to 618 ns to LOW Level Output B tPHZ Output Disable Time GAB to 110 ns from HIGH Level Output B tPLZ Output Disable Time GAB to 216 ns from LOW Level Output B |
类似零件编号 - DM74ALS652 |
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类似说明 - DM74ALS652 |
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