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AM49PDL127BH85IS 数据表(PDF) 11 Page - SPANSION

部件名 AM49PDL127BH85IS
功能描述  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
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制造商  SPANSION [SPANSION]
网页  http://www.spansion.com
标志 SPANSION - SPANSION

AM49PDL127BH85IS 数据表(HTML) 11 Page - SPANSION

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December 16, 2003
Am49PDL127BH/Am49PDL129BH
9
ADV ANCE
I N FO RMAT I O N
PIN DESCRIPTION
A20–A0
= 21 Address Inputs (Common)
A21
= Address Inputs (Flash)
A22
= Address Input (PDL127 only)
(Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash)
CE#f2
= Chip Enable 2 (Flash)
(PDL 129 only)
CE#1ps
= Chip Enable 1 (pSRAM)
CE2ps
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output and open drain.
When RY/BY# = V
IH, the device is
ready to accept read operations and
commands. When RY/BY# = V
OL,
the device is either executing an em-
bedded algorithm or the device is
executing a hardware reset opera-
tion.
UB#s
= Upper Byte Control (pSRAM)
LB#s
= Lower Byte Control (pSRAM)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Write Protect/Acceleration Input.
When WP/ACC#= V
IL, the highest
and lowest two 4K-word sectors are
write protected regardless of other
sector protection configurations.
When WP/ACC#= V
IH, these sector
are unprotected unless the DYB or
PPB is programmed. When
WP/ACC#= 12V, program and erase
operations are accelerated.
V
CCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CCs
= pSRAM Power Supply
V
SS
= Device Ground (Common)
NC
= Pin Not Connected Internally
LOGIC SYMBOL
21
16
DQ15–DQ0
A20–A0
CE#f1
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
A21
LB#s
CE#1ps
CE2ps
CE#f2 (PDL129 Only)
A22 (PDL127 Only)


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