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AM29PDL128G80PEK 数据表(PDF) 7 Page - Advanced Micro Devices |
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AM29PDL128G80PEK 数据表(HTML) 7 Page - Advanced Micro Devices |
7 / 71 page 6 Am29PDL128G October 28, 2004 P R E L IM IN A R Y PRODUCT SELECTOR GUIDE Note: See “AC Characteristics” on page 53 for full specifications. BLOCK DIAGRAM Notes: 1. In double word mode, input/outputs are DQ31-DQ0, address range is A21-A0. In word mode, input/outputs are DQ15-DQ0, address range is A21-A-1. 2. RY/BY# is an open drain output. Part Number Am29PDL128G Speed Option Voltage Range: VCC = 3.0–3.6 V 70R Voltage Range: VCC = 2.7–3.6 V 70 80 90 Max Access Time, ns (t ACC)70 80 90 Max CE# Access, ns (t CE)70 80 90 Max Page Access, ns (t PACC)25 30 35 Max OE# Access, ns (t OE)25 30 40 VCC VSS State Control Command Register PGM Voltage Generator VCC Detector Timer Erase Voltage Generator Input/Output Buffers Sector Switches Chip Enable Output Enable Logic Y-Gating Cell Matrix Y-Decoder X-Decoder Data Latch RESET# RY/BY# (Note 2) STB STB A21–A2 A1–A0 (A-1) A3, A4 CE# OE# WE# DQ31–DQ0 VIO |
类似零件编号 - AM29PDL128G80PEK |
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类似说明 - AM29PDL128G80PEK |
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