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CD82C37A 数据表(PDF) 10 Page - Intersil Corporation |
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CD82C37A 数据表(HTML) 10 Page - Intersil Corporation |
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10 / 24 page  10 FN2967.2 March 20, 2006 82C37A both be ones. See the following diagram and Figure 4 for Mode register functions and addresses. Request Register - The 82C37A can respond to requests for DMA service which are initiated by software as well as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are non-maskable and subject to prioritization by the Priority Encoder network. Each register bit is set or reset separately under software control. The entire register is cleared by a Reset or Master Clear instruction. To set or reset a bit, the software loads the proper form of the data word. See Figure 4 for register address coding, and the following diagram for Request register format. A software request for DMA operation can be made in block or single modes. For memory-to-memory transfers, the software request for channel 0 should be set. When reading the Request register, bits 4-7 will always read as ones, and bits 0-3 will display the request bits of channels 0-3 respectively. Mask Register - Each channel has associated with it a mask bit which can be set to disable an incoming DREQ. Each mask bit is set when its associated channel produces an EOP if the channel is not programmed to Autoinitialize. Each bit of the 4-bit Mask register may also be set or cleared separately or simultaneously under software control. The entire register is also set by a Reset or Master clear. This disables all hardware DMA requests until a Clear Mask Register instruction allows them to occur. The instruction to separately set or clear the mask bits is similar in form to that used with the Request register. Refer to the following diagram and Figure 4 for details. When reading the Mask register, bits 4-7 will always read as logical ones, and bits 0-3 will display the mask bits of channels 0-3, respectively. The 4 bits of the Mask register may be cleared simultaneously by using the Clear Mask Register command (see software commands section). All four bits of the Mask register may also be written with a single command. Status Register - The Status register is available to be read out of the 82C37A by the microprocessor. It contains information about the status of the devices at this point. This information includes which channels have reached a terminal count and which channels have pending DMA requests. Bits 0-3 are set every time a TC is reached by that channel or an external EOP is applied. These bits are cleared upon RESET, Master Clear, and on each Status Read. Bits 4-7 are set whenever their corresponding channel is requesting service, regardless of the mask bit state. If the mask bits are set, software can poll the Status register to determine which channels have DREQs, and selectively clear a mask bit, thus allowing user defined service priority. Status bits 4-7 are updated while the clock is high, and latched on the falling Mode Register 7 6543210 BIT NUMBER 00 01 10 11 XX Channel 0 select Channel 1 select Channel 2 select Channel 3 select Readback 00 01 10 11 XX Verify transfer Write transfer Read transfer Illegal If bits 6 and 7 = 11 0 1 Autoinitialization disable Autoinitialization enable 0 1 Address increment select Address decrement select 00 01 10 11 Demand mode select Single mode select Block mode select Cascade mode select Request Register 7 6543210 BIT NUMBER 00 01 10 11 Select Channel 0 Select Channel 1 Select Channel 2 Select Channel 3 0 1 Reset request bit Set request bit Don’t Care, Write Bits 4-7 All Ones, Read Mask Register 76543210 BIT NUMBER 00 01 10 11 Select Channel 0 mask bit Select Channel 1 mask bit Select Channel 2 mask bit Select Channel 3 mask bit 0 1 Clear mask bit Set mask bit 76543210 BIT NUMBER 0 1 Clear Channel 0 mask bit Set Channel 0 mask bit 0 1 Clear Channel 1 mask bit Set Channel 1 mask bit 0 1 Clear Channel 2 mask bit Set Channel 2 mask bit 0 1 Clear Channel 3 mask bit Set Channel 3 mask bit Don’t Care Don’t Care, Write All Ones, Read 82C37A |
类似零件编号 - CD82C37A |
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类似说明 - CD82C37A |
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