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SY10EL34 数据表(PDF) 4 Page - Micrel Semiconductor

部件名 SY10EL34
功能描述  5V/3.3V 첨2, 첨4, 첨8 CLOCK GENERATION CHIP
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制造商  MICREL [Micrel Semiconductor]
网页  http://www.micrel.com
标志 MICREL - Micrel Semiconductor

SY10EL34 数据表(HTML) 4 Page - Micrel Semiconductor

  SY10EL34_06 Datasheet HTML 1Page - Micrel Semiconductor SY10EL34_06 Datasheet HTML 2Page - Micrel Semiconductor SY10EL34_06 Datasheet HTML 3Page - Micrel Semiconductor SY10EL34_06 Datasheet HTML 4Page - Micrel Semiconductor SY10EL34_06 Datasheet HTML 5Page - Micrel Semiconductor  
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4
Precision Edge®
SY10EL34/L
SY100EL34/L
Micrel, Inc.
M9999-031006
hbwhelp@micrel.com or (408) 955-1690
TIMING DIAGRAM
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers
will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs
will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
EN
Q1
Q2
CLK
Internal Clock
Disabled
Internal Clock
Enabled
Q0


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