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SY10EL34 数据表(PDF) 4 Page - Micrel Semiconductor |
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SY10EL34 数据表(HTML) 4 Page - Micrel Semiconductor |
4 / 5 page 4 Precision Edge® SY10EL34/L SY100EL34/L Micrel, Inc. M9999-031006 hbwhelp@micrel.com or (408) 955-1690 TIMING DIAGRAM The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. EN Q1 Q2 CLK Internal Clock Disabled Internal Clock Enabled Q0 |
类似零件编号 - SY10EL34_06 |
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类似说明 - SY10EL34_06 |
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