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CAT1163WI-25 数据表(PDF) 4 Page - Catalyst Semiconductor |
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CAT1163WI-25 数据表(HTML) 4 Page - Catalyst Semiconductor |
4 / 14 page CAT1163 Doc. No. 3003 Rev. E 4 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice WRITE CYCLE LIMITS Symbol Parameter Min Typ Max Units tWR Write Cycle Time 10 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. RESET CIRCUIT CHARACTERISTICS Symbol Parameter Min Typ Max Units tGLITCH Glitch Reject Pulse Width 100 ns VRT Reset Threshold Hystersis 15 mV VOLRS Reset Output Low Voltage (IOLRS=1mA) 0.4 V VOHRS Reset Output High Voltage VCC - 0.75 V Reset Threshold (VCC=5V) (CAT1163-45) 4.50 4.75 Reset Threshold (VCC=5V) (CAT1163-42) 4.25 4.50 Reset Threshold (VCC=3.3V) (CAT1163-30) 3.00 3.15 Reset Threshold (VCC=3.3V) (CAT1163-28) 2.85 3.00 VTH Reset Threshold (VCC=3V) (CAT1163-25) 2.55 2.70 V tPURST Power-Up Reset Timeout 130 270 ms tWP Watchdog Period 1.6 sec tRPD VTH to RESET Output Delay 5 µs VRVALID RESET Output Valid 1 V |
类似零件编号 - CAT1163WI-25 |
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类似说明 - CAT1163WI-25 |
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