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CAT25C128VA-GT3 数据表(PDF) 10 Page - Catalyst Semiconductor |
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CAT25C128VA-GT3 数据表(HTML) 10 Page - Catalyst Semiconductor |
10 / 12 page CAT25C128/256 10 Document No. 1018, Rev. I CS SCK HOLD SO tCD tHD tHD tCD tLZ tHZ HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) — ——— Figure 9. HOLD HOLD HOLD HOLD HOLD Timing Figure 10. WP WP WP WP WP Timing tCSH SCK WP tWPS tWPH Note: Dashed Line= mode (1, 1) — ——— DESIGN CONSIDERATIONS If an invalid op code is received, no data will be shifted into the CAT25C128/256, and the serial output pin (SO) will remain in a high impedence state until the falling edge of CS is detected again. When powering down, the supply should be taken down to 0V, so that the CAT25C128/256 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT25C128/256 can be reset by refreshing the contents of the Status Register (See Application Note AN10). The CAT25C128/256 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C128/256 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and program-ming is continued. On power up, SO is in a high impedance. |
类似零件编号 - CAT25C128VA-GT3 |
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类似说明 - CAT25C128VA-GT3 |
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