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MC100LVELT22DR2G 数据表(PDF) 1 Page - ON Semiconductor |
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MC100LVELT22DR2G 数据表(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 5 1 Publication Order Number: MC100LVELT22/D MC100LVELT22 3.3VDual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the LVELT22 makes it ideal for applications which require the translation of a clock and a data signal. Features • 350 ps Typical Propagation Delay • <100 ps Output−to−Output Skew • Flow Through Pinouts • The 100 Series Contains Temperature Compensation • LVPECL Operating Range: VCC = 3.0 V to 3.8 V with GND = 0 V • When Unused TTL Input is left Open, Q Output will Default High • Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAMS* KR22 ALYW G G SOIC−8 D SUFFIX CASE 751 1 8 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION http://onsemi.com KVT22 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 (Note: Microdot may be in either location) A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package |
类似零件编号 - MC100LVELT22DR2G |
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类似说明 - MC100LVELT22DR2G |
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