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CAT25C256VI-1.8-GT3 数据表(PDF) 6 Page - Catalyst Semiconductor |
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CAT25C256VI-1.8-GT3 数据表(HTML) 6 Page - Catalyst Semiconductor |
6 / 12 page CAT25C128/256 6 Document No. 1018, Rev. I Protected Unprotected Status WPEN WP WP WP WP WP WEL Blocks Blocks Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable WRITE PROTECT ENABLE OPERATION WP WP WP WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. HOLD HOLD HOLD HOLD HOLD: Hold The HOLD pin is used to pause transmission to the CAT25C128/256 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to Vcc or tied to Vcc through a resistor. Figure 9 illustrates hold timing sequence. STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C128/ 256 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile. Status Register Bits Array Address Protection BP1 BP0 Protected 0 0 None No Protection 0 1 25C128: 3000-3FFF Quarter Array Protection 25C256: 6000-7FFF 1 0 25C128: 2000-3FFF Half Array Protection 25C256: 4000-7FFF 1 1 25C128: 0000-3FFF Full Array Protection 25C256: 0000-7FFF BLOCK PROTECTION BITS 76543210 WPEN X X X BP1 BP0 WEL RDY STATUS REGISTER |
类似零件编号 - CAT25C256VI-1.8-GT3 |
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类似说明 - CAT25C256VI-1.8-GT3 |
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