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CAT25320YIT3 数据表(PDF) 9 Page - Catalyst Semiconductor |
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CAT25320YIT3 数据表(HTML) 9 Page - Catalyst Semiconductor |
9 / 16 page CAT25320 © 2007 Catalyst Semiconductor, Inc. 9 Doc. No. 1111 Rev. E Characteristics subject to change without notice SCK SI SO 00 00 0 01 1 BYTE ADDRESS* 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 * Please check the Byte Address Table (Table 5). CS DATA OUT MSB HIGH IMPEDANCE AN A0 OPCODE READ OPERATIONS Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16-bit address (see Table 5 for the number of significant address bits). After receiving the last address bit, the CAT25320 will respond by shifting out data on the SO pin (as shown in Figure 8). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS ¯¯ high. Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25320 will shift out the contents of the status register on the SO pin (Figure 9). The status register may be read at any time, including during an internal write cycle. Figure 8. READ Timing Note: Dashed Line = mode (1, 1) - - - - - - Figure 9. RDSR Timing Note: Dashed Line = mode (1, 1) - - - - - - 01 2 3 4 5 6 78 10 911 12 13 14 SCK SI DATA OUT MSB HIGH IMPEDANCE OPCODE SO 7 6 5 4 3 2 1 0 CS 00 0 00 1 0 1 |
类似零件编号 - CAT25320YIT3 |
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类似说明 - CAT25320YIT3 |
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