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M4Z28-BR00SH 数据表(PDF) 8 Page - STMicroelectronics

部件名 M4Z28-BR00SH
功能描述  4 Mbit (512 Kbit x 8) ZEROPOWER SRAM
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M4Z28-BR00SH 数据表(HTML) 8 Page - STMicroelectronics

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Operating modes
M48Z512A M48Z512AY M48Z512AV
8/24
2
Operating modes
The M48Z512A/Y/V also has its own Power-fail Detect circuit. The control circuitry
constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out
of tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security
in the midst of unpredictable system operation brought on by low VCC. As VCC falls below
the switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
The ZEROPOWER® RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
WRITEs that can be performed.
2.1
READ mode
The M48Z512A/Y/V is in the READ mode whenever W (WRITE Enable) is high and E (Chip
Enable) is low. The device architecture allows ripple-through access of data from eight of
4,194,304 locations in the static storage array. Thus, the unique address specified by the 19
Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E (Chip Enable) and G (Output Enable)
access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time
(tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the
outputs are activated before tAVQV, the data lines will be driven to an indeterminate state
until tAVQV. If the Address Inputs are changed while E and G remain low, output data will
remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next
Address Access.
Table 3.
Operating modes(1)
1.
See Table 11 on page 17 for details.
Mode
VCC
E
G
W
DQ0-DQ7
Power
Deselect
4.75 to 5.5V
or
4.5 to 5.5V
or
3.0 to 3.6V
VIH
X
X
High Z
Standby
WRITE
VIL
XVIL
DIN
Active
READ
VIL
VIL
VIH
DOUT
Active
READ
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)
(2)
2.
X = VIH or VIL; VSO = battery back-up switchover voltage.
X
X
X
High Z
CMOS standby
Deselect
≤ V
SO
(2)
X
X
X
High Z
Battery back-up mode


类似零件编号 - M4Z28-BR00SH

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类似说明 - M4Z28-BR00SH

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